Designed circuits in 0.13 um CMOS technology for a 3-10GHz UWB CMOS RFIC transceiver with 500 MHz channel bandwidth.

• Modified a 7 Pole Butterworth low-pass Sallen-Key filter with a 264 MHz bandwidth. Debugged the schematic and post layout simulations. Redesigned the poles to account for the effect of RLC parasitic. Simulated the corners by writing Ocean scripts. Analyzed the stability of the gm-constant circuit. Modified digital control unit to address the power downs, glitches, etc.

• Designed a 1.6 GHz divide-by-3 circuit with %50 duty cycle using TSPC D flip-flops. Verified corner and post layout simulations.
• Designed a high frequency differential-to-single-ended circuit and vice versa with multiplexing capability and proper power downs.
• Performed PSS and PNOISE simulations for multiplexed array of wideband current-mode-logic (CML) dividers for four different high frequency PLLs. Evaluated the tail current mismatch.